The MC10129 data inputs are compatible with, and accept TTL logic levels as well as levels compatible with IBMtype buses. The clock, strobe, and reset inputs accept MECL 10,000 logic levels.
The data inputs accept the bus levels, and storage elements are provided to yield temporary latch storage of the information after receiving it from the bus.
The outputs can be strobed to allow accurate synchronization of signals and/or connection to MECL 10,000 level buses. When the clock is low, and the reset input is disabled, the outputs will follow the D inputs. The latches will store the data on the rising edge of the clock. The outputs are enabled when the strobe input is high. Unused D inputs must be tied to VCC or Gnd. The clock, strobe, and reset inputs each have 50 k ohm pulldown resistors to VEE. They may be left floating, if not used.
The MC10129 will operate in either of two modes. The first mode is obtained by tying the hysteresis control input to VEE. In this mode, the input threshold points of the D inputs are fixed. The second mode is obtained by tying the hysteresis control input to ground. In this mode, input hysteresis is achieved as shown in the test table. This hysteresis is desirable where extra noise margin is required on the D inputs. The outer input pins are unaffected by the mode of operation used.
The MC10129 is especially useful in interface applications for central processors, minicomputers, and peripheral equipment.
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